This invention relates generally to programmable logic array (PLA) devices and more particularly, it relates to an interface circuit for interfacing between the "OR-Tied" connection of a PLA device and the phase splitter transistor of a TTL output buffer so as to provide a high speed of operation over a wide range of temperature variations.
As is generally known, arrays for performing logic functions are typically referred to as logic arrays or programmable logic arrays (PLAs) and have been used in recent years to replace random logic in many digital circuits. Such programmable logic arrays are especially useful in the control section of digital systems and are frequently thought of as read-only storage, read-only memories, or the like. The programmable logic array is a well known conventional way of using arrays of identical circuit elements to implement arbitrary logic function in integrated circuits.
A simplified schematic circuit diagram of a TTL programmable logic array device 10 with a Schottky diode array structure 12 of the prior art is shown in FIG. 1 and has been labeled "Prior Art." One of the major problems experienced in this prior art PLA device 10 is that extra propagation delays are encountered due to the double inversion in the buffer 34 having the two inverter stages. This buffer stage is required to properly interface the "OR-tied" to the output buffer and provide necessary level and drive to the output stage 36 over operating temperature range.
The interface circuit 110 of the present invention for use between the "OR-tied" connected of a PLA device and the phase splitter transistor of a TTL output buffer is an improvement over the one of FIG. 1 and exhibits a high speed of operation over a wide range of temperature variations. This is achieved by the elimination of the buffer 34 having the two inverter stages so that the output of the sensing circuit 26 is connected directly to the phase splitter transistor Q2 of the output buffer 36. Since the beta (current gain) of the phase splitter transistor Q2 will increase with temperature, a smaller current drive is required at the higher temperatures. Two independent bandgap generators with opposite temperature coefficients are provided so as to generate a resultant base drive current to the phase splitter transistor Q2 which is greater at the lower temperature of -55.degree. C. and is less at the high temperature of +155.degree. C., thereby maintaining a high switching speed over the temperature range.